1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a semiconductor memory device inputting and outputting high frequency data by using data parallel/serial conversion.
2. Description of the Background Art
It has been necessary in recent years that the data band widths of semiconductor devices be increased to keep pace with the higher operating frequencies of microprocessors. Publicly known techniques increase the data band width by multiplying the data bus width or raising the clock frequency of a synchronous semiconductor memory device. As a technique of inputting and outputting data at high speed, such a synchronous semiconductor memory device has been proposed that inputs and outputs data in synchronization with both rising and falling edges of a clock signal.
However, achievement of a higher data input/output frequency is limited by access time for a DRAM (Dynamic Random Access Memory) as a memory device. In order to solve this problem, an interface technique has been made public which employs parallel/serial conversion of data so as to increase the frequency of a synchronous clock signal for transmitting input/output data to and from an external unit higher than the internal operating frequency of the DRAM.
FIG. 14 is a schematic block diagram showing a configuration of a conventional semiconductor memory device 500 allowing higher speed interfacing by using data parallel/serial conversion.
Referring to FIG. 14, semiconductor memory device 500 includes a clock terminal 5 receiving a clock signal CLK, a control signal node Ncc receiving a control signal for controlling an operation of semiconductor memory device 500, a memory core portion 20, and a data input/output control portion 40.
Semiconductor memory device 500 further includes a control circuit 10 for controlling operations of memory core portion 20 and data input/output control portion 40 according to a control signal RQ received from control signal node Ncc and clock signal CLK received from clock terminal 5.
Memory core portion 20 operates according to an address signal and command control signals generated by control circuit 10. Memory core portion 20 includes a plurality of memory mats MT0 to MTn (n is a natural number). For each of memory mats MT0 to MTn, m pieces of data (m is a natural number) can be read and written in parallel. In FIG. 14, m=8.
Data input/output control portion 40 performs parallel/serial conversion of data from eight pieces of parallel data input/output for each memory mat into one serial data transmitted by each data node Nd0 to Ndn, and vice versa. Data input/output control portion 40 operates according to data I/O control signals generated by control circuit 10. Data nodes Nd0 to Ndn can transmit data to and from other circuit devices and external units.
Data input/output control portion 40 includes data conversion circuits 50-0 to 50-n and input/output buffers 60-0 to 60-n provided corresponding to memory mats MT0 to MTn.
In outputting data, each of data conversion circuits 50-0 to 50-n converts eight pieces of parallel data output from each memory mat to serial data. Output buffers 60-0 to 60-n output the serial data transmitted from data conversion circuits 50-0 to 50-n as data DQ0 to DQn from data nodes Nd0 to Ndn.
For data input/output control portion 40, only an operation concerning outputting (reading) data will be described in detail. With inputting (writing) data, serial input data input from data nodes Nd0 to Ndn are transmitted through input/output buffers 60-0 to 60-n to data conversion circuits 50-0 to 50-n and the serially input data are converted to parallel data by the data conversion circuits, so that the data can be written to corresponding memory mats in parallel.
The command control signal for controlling memory core portion 20 and the data I/O control signal for controlling data input/output control portion 40, both of which are generated by control circuit 10, are signals based on different frequencies. The frequency of the memory core portion is suppressed low so that it can operate stably as a DRAM, and one data reading/writing operation for the memory core portion is performed in parallel for a plurality of data.
Then, a plurality of data which are read/written in parallel from/to the memory core portion are converted to serial data and successively input/output by the data input/output control portion capable of a high frequency operation. It is therefore possible to attain a high speed operation as the entire semiconductor memory device.
FIG. 15 is a conceptual diagram illustrating data parallel/serial conversion during outputting data in semiconductor memory device 500.
Referring to FIG. 15, one reading operation causes memory mat MT0 to output eight pieces of data DT0&lt;0&gt; to DT0&lt;7&gt; in parallel. In the following, a plurality of data simultaneously processed in parallel are also referred to as a multiple-bit signal collectively. For example, DT0&lt;0&gt; to DT0&lt;7&gt; are also collectively referred to as DT0&lt;0:7&gt;. Similarly, the nth memory mat MTn outputs DTn&lt;0:7&gt; in parallel.
As an example, data outputting from memory mat MT0 will be described. Eight pieces of data DT0&lt;0:7&gt; which are simultaneously read out from memory mat MT0 in parallel are input to data conversion circuit 50-0 in parallel.
Data conversion circuit 50-0 outputs the parallel data one by one in series to input/output buffer 60-0 according to a data input/output control clock CLKIO which is one of data I/O control signals generated by control circuit 10. Output buffer 60-0 outputs data DQ0 to data node Nd0 according to signal level output from data conversion circuit 50.
Similarly, for other memory mats, parallel/serial conversion of data is carried out by data conversion circuits 50-1 to 50-n and output buffers 60-1 to 60-n, and data can be output from data nodes Nd1 to Ndn at a frequency higher than the operating frequency of the memory core portion.
FIG. 16 is a timing chart illustrating data outputting of semiconductor memory device 500.
Referring to FIG. 16, data is input and output at data nodes Nd0 to Ndn in response to both rising and falling edges of data input/output control clock CLKIO.
In semiconductor memory device 500, data nodes Nd0 to Ndn are provided for memory mats MT0 to MTn, respectively. Therefore, data nodes Nd0 to Ndn deal with data which are input/output in parallel for corresponding memory mats. For example, data DQ0 transmitted at data node Nd0 is data associated with memory mat MT0.
In outputting data, data DT0&lt;0:7&gt; to DTn&lt;0:7&gt; read out in parallel from the memory mats prior to clock activation timing at time T0 are output in series from the data nodes for clock activation edges at time T0 to T7.
As described above, by performing one reading/writing operation of the memory core portion which constitutes a DRAM in parallel for a plurality of data and by inputting/outputting data to/from an external unit using parallel/serial conversion of data, data can be input and output at a frequency higher than the operating frequency of the memory core portion. Thus, the data input/output cycle that is limited by the access time of a DRAM which forms a memory core portion can be further shortened, and the number of data which are input/output in parallel for the memory core portion during one reading/writing operation can be increased, which allows a higher frequency operation as the entire semiconductor memory device.
However, in attaining the higher frequency operation of a semiconductor memory device, a device for testing the semiconductor memory device itself hereinafter, also referred to as a memory tester) also requires higher performance which enables a higher frequency. Thus, the memory tester to be used becomes expensive. Therefore, in the semiconductor memory device for performing a high frequency operation using parallel/serial conversion of data, cost reduction for an operational test is important.